This signal is typically uni-directional, although a target can get more time to respond to a request, if needed, by holding both SCL and SDA low while generating an ACK. The SCL line controls the speed of data communication over the bus. ![]() Targets also use the SDA line to acknowledge correct reception of the request (ACK) by holding SDA low or deny correct reception (NACK) by letting SDA be pulled high. The target returns the requested data over the SDA line. The controller uses the SDA line to select the target to be addressed and the register to access within that target. The controller has open-collector I/Os that can pull the serial data (SDA) and clock (SCL) lines low and needs a pull-up resistor, which allows multiple controllers and targets to co-exist without causing bus contention. The I2C bus usually has one controller, such as an MCU or SoC, and one or more target devices. The standard specifies a two-wire connection comprising bi-directional data and clock lines, which can be implemented cost-effectively.I2C’s simplicity and efficiency have seen the underlying communication principles embodied in standards such as SMBbus and PMBus. Originally intended for short range, board level communication, its success has seen applications multiply and the maximum data-handling capability extend to include 100kHz standard mode, 1MHz fast mode plus and 5MHz ultra-fast mode plus. The inter-integrated circuit I2C bus was introduced in the 1980s to enable communication between a host CPU and peripheral devices for configuration, monitoring and control. ![]() I2C-bus applications sometimes require high voltage isolation to ensure safety and reliability.
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